CPU QuickLinks
Chipset QuickLinks
Video QuickLinks
Software QuickLinks

20XX
Q4 2008
Q3 2008
Q2 2008
Q1 2008
Q4 2007
Q3 2007
Q2 2007
Q1 2007
Q4 2006
Q3 2006
Q2 2006
Q1 2006
Q4 2005
Q3 2005
Q2 2005
Q1 2005
Q4 2004
Q3 2004
Q2 2004
Q1 2004
Q4 2003
Q3 2003
Q2 2003
Q1 2003
Q4 2002
Q3 2002
Q2 2002
Q1 2002
Q4 2001
Q3 2001
Q2 2001
Q1 2001
Q4 2000
Q3 2000
Q2 2000
Q1 2000
Q4 1999
Q3 1999
Q2 1999
Q1 1999




mike@mikeshardware.co.uk

Q4 2000

Previous Quarter   Next Quarter

10/00

ATI Radeon SDR (RV100 core) was released in October. This SDR verison of the DDR Radeon 256 will run at a clock and memory speed of 166Mhz (less than the Retail Radeon at 183Mhz, but the same as an OEM Radeon). Unlike nVidia's GeForce2MX (175Mhz core, 166Mhz SDR memory), which is a cut down version of the GeForce2 core, the Radeon core has not been changed for this Value oriented product. Initial benchmarks show that the GeForce2 MX tends to be faster under lower resolution (1024x768x32 or less) conditions, but Radeon's HyperZ technology (providing extra memory bandwidth) allows it to beat the MX at higher resolutions. Currently Windows 2000 drivers are an issue, providing just 50% of the performance of the Windows 9x drivers (this has since been largely fixed).

nVidia GeForce2 Pro was released in October. The GeForce2 Pro is positioned between the GeForce2 GTS and GeForce2 Ultra, featuring the 200Mhz core clock of the GTS model, but combined with faster 200Mhz DDR memory (GTS has 166Mhz DDR and the Ultra has 230Mhz DDR). Although the raw fillrate of the Pro is equivalent to the GTS, the main bottleneck of the GeForce2 GTS is its memory bandwidth. The GeForce2 Pro therefore performs roughly mid way between the GeForce2 Ultra and the GeForce2 GTS.

Intel Pentium III Xeon 1Ghz with 256Kb of L2 cache was released in October.

Intel Itanium, formally known as Merced, is the first Intel processor based around the new IA-64 architecture co developed by Intel and Hewlett-Packard. Itanium has been rolled out under a pilot release scheme in October at a clock speeds of 733Mhz, although the platform release is not due until Q2 2001. The Itanium processor is aimed at the Server market and as such is likely to be very expensive, much like the high-end Xeons of today.

Although Itanium will be able to natively execute IA-32 instructions (x86 code), the architecture is designed around the EPIC (Explicit Parallel Instruction Computing) philosophy and its new 64bit instruction set. One of the most difficult problems faced by current generation processors is that of keeping the processors instruction pipelines filled with data. In order to prevent pipeline stalls the CPU must dedicate a large amount of logic (and hence transistors) to the task of finding inherent parallelism in the code and accurately predicting branch instructions. The IA-64 architecture is designed to shift the job of keeping the processors instruction pipeline filled from the processor itself to the compiler. As the compiler has access to the entire program code, rather than the short instruction stream visible to the CPU, it should be able to find considerably more parallelism than would normally be the case.  For this reason the Itanium can issue up to 6 instructions per clock cycle through its 10 stage pipeline (2 EPIC bundles with 3 instructions per bundle). In order to keep the pipelines filled Itanium features 128 Integer/Multimedia registers, 128 82-bit Floating Point registers, 64 predicate registers, and 8 Branch Registers. The architecture also features 2 integer/MMX units, 2 FMACs (floating-point multiply-and-accumulate units), 2 SP FMACs for SSE and 2 load/store units. Itanium's cache architecture features a 16Kb data and 16Kb L1 instruction cache along with a 96Kb unified L2 cache and up to 4Mb of full-speed Level 3 cache (off chip). The option of 2Mb of L3 cache will also be available. This 25 million transistor CPU also has support for clustering up to 512 processors.

The CPU will be based on Intel's PAC418 (418-pin) Multi Chip Module (MCM) Socket package.

Intel 460GX chipset is designed for use with the Itanium, and was launched under Itanium's Pilot release in October. The 460GX features a double-pumped 133Mhz bus capable of 266MT/s (Million Transactions per second), and support for up to 4 processors. The i460GX also supports PC100 SDRAM and PC1600 DDR SDRAM. RDRAM will not be supported due to its significant price premium and the fact that machines built around Itanium are likely to require vast quantities of memory.

Microsoft Office:Mac 2001 was released on October 11th for the Macintosh platform. In addition to updated versions of Word, Excel and Powerpoint, Office:Mac 2001 ships with the Mac equivalent of Outlook called Entourage.

Intel Price Cuts on the lower end Pentium III processors occurred on October 15th. See the CPU Prices page for additional information.

AMD Thunderbird 1.2Ghz was released on October 17th.

AMD Duron 800 was released on October 17th.

Intel i815M chipset was released on October 23rd. The i815M is the mobile version of the desktop i815 chipset.

Intel i815EP chipset was released in Mid October. The i815EP is essentially an i815E without the integrated i752 graphics and is priced between the i815 and i815E. Later versions of the i815EP will include a new MCH for Tualatin support (Q2 2001).

Microsoft Office XP Beta 2, formally known as Office 10, was released on October 24th. See the final release Roadmap entry for additional information.

Microsoft MSN Explorer was released on October 25th.

Sony Playstation II was released in the US on October 26th. See the Q1 2000 Roadmap entry for additional information on PS2.

Intel Price Cuts occured on October 29th. See the CPU Prices page for additional information.

AMD Thunderbird 1Ghz, 1.13Ghz & 1.2Ghz on a 266Mhz FSB (133 x 7.5/8.5/9) were released on October 30th.

AMD 760 chipset was released on October 30th, although noise problems between the memory controller and CPU, when the FSB is at 266Mhz, have meant that motherboards will not be available until the start of January. The AMD760 features support for PC1600 (200Mhz FSB) and PC2100 (266Mhz FSB) DDR SDRAM for use with Thunderbird and Mustang processors. Other features of the chipset include AGP4X, 4 USB ports, 8Gb addressing with 4 DIMM's and ATA-100 support.

Windows XP Beta 1, formally known as Whistler, was released in its Professional version on October 31st. Beta 1 is available in both 32-bit and 64-bit (Itanium) versions and features the new 'skinable' user interface along with enhanced ease of use and vastly improved boot times (around 10 seconds) with new hardware.

11/00

Internet Explorer 5.5 SP1 was released on November 3rd.

ATI Radeon SE was announced on November 9th, with board availability expected in February 2001. The Radeon SE is aimed at the value segment, featuring a lower clock speed than the standard Radeon cards (150Mhz rather than 166 or 183Mhz) and no HyperZ support (this is disabled in the drivers and can be enabled with a registry hack - see the Hardware Tips page for details). Due to the lower clock speed, the Radeon SE does not feature a Fan on the heatsink. Apart from the lower clock speed, the hardware is identical to that of a standard Radeon, featuring 2 pixel pipelines with 3 texturing units per pipeline.

DirectX 8 was released in November 11th. Features include the consolidation of the DirectSound/DirectMusic and DirectDraw/Direct3D interfaces, support for vertex and pixel shaders, IP voice comms in DirectPlay, Microsoft TV Technologies support (digital TV), WMA and WMV read/write routines in DirectShow and DLS audio synthesis support.

Intel Celeron 733 & 766 were released on November 13th.

Netscape Communicator 6 was released in Mid November.

Intel Pentium 4, formally known as Willamette, was released on November 20th at 1.4 and 1.5Ghz, following delays caused by problems with the i850 chipset. The Pentium 4 has an enhanced instruction set (SSE-2), featuring 144 new instructions including the addition of double-precision SIMD extensions to SSE and 128bit MMX instructions. Willamette's architecture has been christened 'Netburst' and features a very deep 20 stage pipeline (the current P6 core has a 10 stage pipeline). In order to prevent very costly pipeline stalls, Willamette features a trace cache capable of holding 12,000 micro-ops along with significantly enhanced branch prediction algorithms. There are two integer units (termed the Rapid Execution Engine by Intel) on the CPU which are 'double pumped'. This means they effectively run at twice the data rate of the rest of the CPU (equivalent to 3Ghz for a 1.5Ghz CPU), although they do not have the latency advantage of being clocked twice as high. This is likely to be performed by utilising both the rising and falling edges of the clock. The die also contains two Floating point units, one of which deals with x87 FP instructions, MMX and SSE-2 while the other manages FP moves and stores. The standard x87 Floating Point performance of the Pentium 4 is rather poor compared with a Pentium III or Athlon and Intel is recommending the use of SSE-2 floating point operations rather than x87 instructions. This is likely to hurt current FP-intensive applications, but is a good long term strategy. Intel's FP performance is considerably worse than that of current RISC processors due to the stack-based, 8 register x87 instruction set. At 1.5Ghz the SSE-2 instruction set could peak at 11.2GFLOPS compared to the 1.4GFLOPS maximum provided by x87. Other features of the architecture include an 8Kb L1 data cache, to complement the Trace Cache, and a 256Kb L2 cache. The L2 cache is able to deliver data every clock cycle, as opposed to every other clock cycle like the Coppermine L2 cache. This means that the memory bandwidth of the L2 cache is double that of an equivalently clocked Pentium III Coppermine, at 40Gb/s as opposed to 24Gb/s for a 1.5Ghz CPU. It should be noted that the L2 cache of the PIII is itself much better than that of the Thunderbird Athlon.

The CPU will be based on Intel's 0.18 micron FC-PBGA package, in a new 432-pin Socket format. The standard (non-Foster) version of the Pentium 4 will not be SMP (Dual processor) capable.

Initial benchmarks have shown that the performance of the P4 varies considerably depending on the application type. Memory intensive applications (e.g. the game Quake 3) perform excellently due to the high memory bandwidth of the dual-channel RDRAM bus. Most other applications, however, perform fairly poorly in comparison to the P3 or Athlon. A 1.2Ghz Athlon tends to beat the P4 in the vast majority of current applications. Of course, the use of SSE2 and enhanced compilers will reduce this discrepancy in the future.

Intel i850 (Tehama) chipset was released on November 20th to complement the Pentium 4. This chipset replaces the ageing GTL+ P6 bus with a new, high performance, 3.2Gb/s (4MT/s, 100Mhz Quad pumped) RDRAM-based bus. The i850 features support for 4 RIMM slots which may contain either PC600 or PC800 RDRAM (2Gb max) along with the 4 USB ports and 2 ATA 100 IDE channels provided by the ICH2 south bridge. The high bandwidth bus finally allows RDRAM's capabilities to be fully utilised -  The Pentium III's 100 and 133Mhz FSB speeds have seriously crippled RDRAM-based chipsets performance.

Sony Playstation II will be released in the UK on November 24th. See the Q1 2000 Roadmap entry for additional information on PS2.

VIA Apollo Pro 266 chipset started to be available in quantity in November.

VIA KM133 chipset started to be available in quantity in November for the AMD platform. The KM133 is essentially a KT133 (AMD Socket A chipset - 200Mhz FSB, 2Gb PC133 SDRAM, ATA100, 4XUSB) with an integrated S3 Savage 4 graphics core. An AGP 4X port is also supported for an optional graphics card upgrade.

VIA KL133 chipset started to be available in quantity in November. for the AMD platform The KL133 is the 'light' version of the KM133, (AMD, SDR) including an integrated Savage 4 graphics core but excluding external AGP support.

VIA PL133 chipset started to be available in quantity in November for the Intel platform. The PL133 is the 'light' version of the PM133 (Intel, SDR), including an integrated Savage 4 graphics core but excluding external AGP support.

Microsoft Visual Studio.NET Beta 1 was released in late Nov.

Microsoft Office 2000 SP2 was released on November 29th. SP2 is available from Microsoft's Office Resource Kit Toolbox.

VIA Cyrix III 650 & 667 CPU's were released on November 30th

12/00

ALI MAGiK 1 chipset for the AMD platform started shipping in the first week of December (although it was announced in July), with the first motherboards expected to be released in early January. The MAGiK 1 chipset supports DDR SDRAM, and initial benchmarks show that performance is slightly worse than AMD's 760 chipset.

VIA KT133A chipset was released on December 8th for the AMD platform The KT133A is a minor modification of the KT133 chipset, giving support for AMD's 266Mhz FSB speed.

Windows 2000 SP2 Beta 1 was released on December 9th.

Intel Price Cuts occurred on December 10th. See the CPU Prices page for additional information.

AMD Price Cuts occurred on December 10th. See the CPU Prices page for additional information.

SiS 635 chipset was announced on December 11th, although was not released until Q1. The 635 is a single chip, DDR capable chipset for the Intel platform. See the SiS 735 Roadmap entry for additional information.

SiS 735 chipset for the AMD platform was announced on December 11th, although availability is not expected until Q3 2001. SiS 735 is a single chip solution, containing both the North and South bridges. The North and South bridges are internally connected by SiS's Multi-threaded I/O link which has a bandwidth of 1.2GB/s. The SiS 735 supports both SDRAM and DDR SDRAM, AGP4X, 6 PCI masters, ATA100, up to 6 USB ports, AC '97 audio/modem, 10/100 Ethernet or 1/10M Home PNA and AMR, ACR or CNR slots. Initial benchmarks have shown this chipset to be fastest Socket A DDR chipset on the market as of early Q3 2001.

SiS 315 graphics chipset was announced on December 11th, with availability expected in Q1 2001 (probably Q3?). The SiS315 chipset has on-board T&L, a 256-bit 3D engine, a DDR memory interface (up to 5.3Gb/s memory bandwidth), Dual display, TV and LCD outputs and DVD motion compensation.

Q4 00

V.92 protocol products are expected to become available in Q4. V.92 improves modem access speeds from v.90's 56Kbps download/33.6Kbps upload to 56Kbps/47Kbps. Additional features include a reduction in handshake time and support for call waiting signals. The v.44 data compression standard is also expected to improve maximum data rates from  the current 150-200Kbps to around 300Kbps.

Previous Quarter   Next Quarter


mikeshardware.co.uk Copyright © 1999-2006 Michael K. Warner. All rights reserved. No part of the content of this web-site may be reproduced in any form without prior written consent. Please send any comments or queries to mike@mikeshardware.co.uk.