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04/01
AMD Duron 900Mhz, based on the Spitfire core, is expected to be released on April 2nd.
Microsoft Office XP was released to manufacturing on April 5th.
Intel Celeron 850, with a 100Mhz FSB speed, was released on April 9th.
Intel Price Cuts occurred on April 15th. See the Intel CPU Prices page for additional information.
AMD Price Cuts were announced on April 16th. See the AMD CPU Prices page for additional information.
Intel Pentium 4 1.7Ghz, based on the Willamette core, was released on April 23rd.
Intel Price Cuts for Pentium 4 CPU's occurred on April 29th. See the Intel CPU Prices page for additional information.
AMD Price Cuts occurred on April 30th. See the AMD CPU Prices page for additional information.
05/01
Intel Pentium III stepping cD0 started shipping on May 1st. Changes include an increase in thermal design power and an increase in core voltage (1.7 to 1.75). The 1Ghz model will be made on the new FC-PGA2 package, originally intended to be debuted with Tualatin. The FC-PGA2 package contains an Integrated Heat Spreader (IHS) which provides a ring around the core of the CPU to prevent any damage which could occur when affixing a Heatsink. The cD0 stepping is intended to increase the yield on high-end PIII CPU's.
MSN Explorer 6.1 was released on May 3rd. Features include a detachable My Places bar, an integrated media player, local news, weather and city information and an enhanced email editor with integrated spell checking for users with Office or Works.
Windows 2000 SP2 was released on May 11th, with official availability from Microsoft of May 16th. Windows 2000 SP2 features a large number of bug fixes, but few new features. Some of my favourite are ATA100 support, DirectCD CD-R reading and official support for PS/2 keyboard hot-swapping. Unfortunately it doesn't look as if my two main annoyances with Windows 2000 will be fixed with this service pack - the Window hierarchy problems and fixing multi-monitor support for single-chip, dual display video cards (e.g. with the Matrox Dual Head video cards - note that this problem has been worked around in the latest Matrox drivers).
PC2400 DDR SDRAM was first announced by Crucial on May 13th. PC2400 offers a peak memory bandwidth of 2.4GB/s over a 300Mhz bus. At this point, however, there are no chipsets available to take advantage of this bus speed.
Mobile Athlon 4 (Palomino) was released on May
14th at clock speeds of 850Mhz, 900Mhz, 950Mhz and 1Ghz, all running
at a core voltage of 1.4v. The Palomino core features six innovations over
the previous Thunderbird core. The first, and perhaps the most important
for future clock-speed ramping, is a reduced power requirement. Heat and
power consumption was a major problem with the Thunderbird core, and the
aim of Palomino is to reduce these to a level which will allow the clock
speed of the Athlon to be safely increased. The Palomino core reduces the
power requirement of the CPU by approximately 20%.
Palomino will also integrate a thermal diode and circuitry into the CPU
for accurate core temperature measurements and thermal control. The
thermal circuitry is expected to behave much like that found in the
Pentium 4 - i.e. it will prevent the CPU overheating by pausing processing
whilst the temperature drops to an acceptable level.
Unlike Thunderbird and Spitfire, the new Athlon and Duron cores will
feature AMD's PowerNow! 2 mobile power saving technology, based around the
PowerNow! technology found in the
mobile K6 processor range. PowerNow! 2 allows the dynamic changing of clock
speed and core voltage, from 500Mhz at 1.2V upwards. 32 speed and voltage
steps are possible, although it is unlikely that such fine granularity
will be used in practice.
In addition to power reduction and thermal controls, Palomino also
includes a number of performance enhancing features. The new core features
a larger L1 cache Translation Lookaside Buffer (TLB), an automatic data
prefetching mechanism and a full SSE implementation. The L1 TLB held 24
virtual to physical memory translations in the Thunderbird core and has
been increased to a currently unknown size with the Palomino core.
Although this increases the memory translation lookup hit rate, it is not
expected to have a great deal of real-world performance benefit. The
prefetching mechanism, which predicts what is needed in the cache &
fetches it from main memory, is expected to provide the highest
performance improvement. The Palomino features an additional 52 3DNow!
instructions, which AMD is refering to as 3DNow! Professional. In fact the
3DNow! instruction set enhancements which came with the original Athlon
were a subset of Intel's SSE instruction set. The new instructions added
to Palomino give the new processor a full SSE implementation. This could
provide benefits to programs which are written with good SSE optimisation,
but a poorer 3DNow! implementation.
Initial benchmark data, provided by AMD, suggests that the Palomino will perform roughly 2-15% faster than an equivalently clocked Thunderbird. Business Winstone 2001 rises by about 5%, Quake III by 6% and Sysmark 2000 by 10%.
AMD Mobile Duron (Morgan) was released on May 14th at clock speeds of 800 and 850Mhz. The Morgan core will replace the Spitfire core of Duron and will be made in Austin, Texas using Aluminium interconnect technology (like Spitfire, but unlike Palomino which will be built in Dresden using Copper interconnects). The Morgan core shares its featureset with the Athlon 4 (Palomino) and therefore includes a reduction in power consumption, an increased size TLB, hardware data prefetching, the SSE instruction set (called 3DNow! Professional), PowerNow! power saving technology and an integrated thermal diode.
nVidia Quadro DCC was released on May 15th. The Quadro DCC is nVidia's workstation GPU based around the GeForce3 core.
VIA KN133 mobile chipset was released on May 15th.This chipset is designed for the Athlon 4 and Mobile Duron CPU's, featuring support for a 200 or 266Mhz FSB speeds and PowerNow! 2 power management technology. The chipset also features integrated Savage4 graphics and DSTN support.
Intel Celeron stepping cD0 is expected to start production on May 16th with mass shipments starting on July 30th. The core voltage of Celeron processors will be raised from 1.7 to 1.75v on 733Mhz+ processors.
Windows Media Player 7.1 was released on May 16th. Media Player 7.1 includes support for Windows Media Audio 8 (WMA8) and Windows Media Video 8 (WMV8).
Mobile Pentium III 750 Low Voltage was released on May 21st.
Mobile Pentium III 600 Ultra Low Voltage was released on May 21st.
Mobile Celeron 800 was released on May 21st.
Mobile Celeron 600 Low Voltage was released on May 21st.
Intel Xeon (Dual Processor), formally known as Foster, is the Dual Processor capable, server version of the Pentium 4 released on May 21st at clock speeds of 1.4, 1.5 and 1.7Ghz. The core is based around the same NetBurst architecture as the Pentium 4. The initial version of the Xeon is identical to the standard Pentium 4 apart from its form factor (microPGA Socket 603) and its dual processor capability. The rumoured Simultaneous Multi Threading functionality (called Jackson technology) is not included in this release of the Xeon, but is expected to be implemented in a forthcoming core.
Intel i860 (Colusa) chipset was released on May 21st to complement Intel's Xeon CPU. The i860 is very similar to the desktop i850 chipset with the addition of dual processor SMP support, 2x64-bit PCI buses (via two PCI64 hub chips known as P64H) and Memory Repeater Hubs (MRH-R) to increase the maximum memory size to 4Gb (8 RIMM's). The i860 also features a prefetch cache to reduce memory latency and help improve bus contention for dual processor systems.
Intel Price Cuts for Pentium III and Celeron CPU's occurred on May 27th. See the Intel CPU Prices page for additional information.
VIA C3 750 was released on May 29th.
Intel Itanium was released on May 29th. The Itanium will initially be available in four different configurations - with a 733Mhz or 800Mhz clock speed and either 4 or 2Mb of L3 cache. For more information see the Itanium pilot release Roadmap entry. Initial synthetic benchmarks have shown the Integer performance to be somewhat lacking, but the Floating Point performance to be the best of any CPU released at this point in time.
Initial prices of the Itanium processors are Itanium 800/4Mb $4227, Itanium 800/4Mb $1980, Itanium 733/4Mb $4227(?) and Itanium 733/2Mb $1177.
Intel 460GX chipset was launched on May 29th. For more information see the Q4 2000 pilot release Roadmap entry.
Windows XP 64bit Edition (Pre-release) for Intel's Itanium processor was released on May 29th. This pre-release version of Windows XP is fully supported by Microsoft. 64bit Windows XP supports a virtual memory size of 16TB (compared to the 32bit version's 4Gb) and a page file of 512TB (from 16TB). Other memory adjustments are as follows, with the first number representing 64bit WinXP and the second number representing 32bit Win2k - Hyperspace: 8Gb/4Mb, Paged Pool: 128Gb/470Mb, Non-paged Pool: 128Gb/256Mb, System Cache: 1TB/1GB, System PTE: 128Gb/660Mb.
Windows Advanced Server Limited Edition 2002 (Pre-release) for Intel's Itanium processor was released on May 29th.
PC2700 DDR SDRAM, made from DDR333 modules, was JEDEC approved on May 30th. The first PC2700 modules are already shipping. PC2700 runs on a 333Mhz bus, giving a peak memory bandwidth of 2.7GB/s.
VIA Apollo Pro 266T chipset was released on May 31st for the Intel P3/Celeron platform. The Apollo Pro 266T is the Tualatin capable version of the Apollo Pro 266 (Intel, DDR). It will also feature the support for up to 4 64-bit 66Mhz PCI slots via an additional VPX chip.
VIA Apollo Pro 133T chipset was released on May 31st for the Intel P3/Celeron platform. The Apollo Pro 133T is the Tualatin capable version of the Apollo Pro 133A (Intel, SDR).
VIA PL133T chipset was released on May 31st for the Intel platform. The PL133T is the Tualatin capable version of the PL133 (Intel, SDR), including an integrated Savage 4 graphics core but excluding external AGP support.
VIA PLE133T chipset iwas released on May 31st for the Intel platform. The PL133T is the Tualatin capable version of the PL133 (Intel, SDR), including an integrated Trident Blade graphics core but excluding external AGP support.
VIA KLE133 chipset was released on May 31st for the AMD platform The KLE133 is a minor modification of the KL133 and the 'light' version of the KM133 (AMD, SDR) including an integrated Trident Blade graphics core but excluding external AGP support.
Microsoft Office XP, formally known as Office 10, was released on May 31st. MS Office XP offers a number of new features over Office 2000, including voice recognition (for dictation and commands), a Windows XP ('Whistler') style interface, task panes for commonly used functionality and a new 'Subscription' license mode (in selected countries, not including the US). Subscription mode will allow the user to 'subscribe' to Office for a certain period of time rather than paying for it outright. This subscription can then be renewed, extending the amount of time the suite can be used. Office XP will also contain anti-piracy measures in its Retail, OEM and MSDN forms. Internet or phone based registration, based on a machine-unique product activation key, will be required before it can be used. Corporations using volume licences will not be affected by this measure.
Pricing is as follows: Standard Edition (Word, Excel, Outlook, PowerPoint) $479/$239 (upgrade), Professional (+Access) $579/$329, Professional Special Edition (+FrontPage & Publisher) $479, Developer $799/$549 (+ SharePoint & developer tools).
06/01
VIA P4X266 chipset, formally known as the PX266, was announced on June 3rd. See the release Roadmap entry for more details about this chipset.
nVidia nForce 220 & 420 chipsets, formally known as Crush 11 and Crush 12 respectively, for the AMD platform were released on June 4th. The first motherboards based around these chipset are expected to appear in November. The nForce family of chipsets will feature an nVidia developed South Bridge along with a North Bridge with integrated NV11 (i.e. GeForce2 MX) graphics. The North and South bridges are connected by AMD's HyperTransport protocol. The HyperTransport bus (formally known as LDT, is an 8bit wide, 400Mhz differential (effectively DDR) bus giving a bandwidth of 800Mb/s between the two chips. With PCI devices, ATA drives, Ethernet, USB, legacy devices and nVidia's APU (Audio Processing Unit built into the South Bridge) all wanting to communicate to main memory via the North Bridge, this extra bandwidth is certainly of use. Data transfer between North and South bridge is also helped by nVidia's StreamThru technology. This data transport system provides isochronous data transfer for devices connected to the South Bridge (APU, ATA, LAN, USB, IEEE1394 etc) giving them a virtual channel of guaranteed bandwidth and latency to main memory.
The North Bridge, or Integrated Graphics Processor (IGP), will be available in two forms - the nForce 220 (codename Crush 11) and the nForce 420 (codename Crush 12). Both products feature support for SDRAM and DDR SDRAM and feature an integrated NV11 (GeForce2 MX) graphics core. The difference between these two North Bridges is in their memory access. The nForce 220 provides a standard 64-bit data path to main memory, whereas the nForce 420 provides a 128-bit data path via nVidia's TwinBank memory architecture. TwinBank is essentially a crossbar switch, featuring two independent 64-bit memory controllers. In order for TwinBank to function, DIMMs are required to be put in pairs. When using TwinBank with PC2100 DDR SDRAM, the bandwidth from North Bridge to memory is 4.2Gb/s. Although this bandwidth cannot all be used by the processor (the EV6 connection between North Bridge and the CPU has a bandwidth of 2.1Gb/s), the remaining bandwidth is used as needed by the integrated graphics controller and South Bridge connected devices. Another feature of the IGP is nVidia's Dynamic Adaptive Speculative Preprocessor (DASP), which improves memory latency between the CPU and main memory. This is performed by monitoring the CPU's data requests to memory to try to determine access patterns and then prefetching data. In essence it behaves like an intelligent, but fairly small, L3 cache. nVidia claim that performance can be improved by up to 20% with the use of the DASP. The Integrated NV11 graphics operates at 175Mhz and contends for memory bandwidth with the CPU and South Bridge connected devices. Performance with the nForce 220 (One memory controller giving 64-bit memory access to DDR SDRAM) is approximately equivalent to the GeForce2 MX 200. When using the nForce 420 North Bridge with TwinBank in operation (128-bit memory access with 2 DDR DIMMs), GPU performance increases to roughly 25% faster than a GeForce2 MX 200. It should be noted that both chipsets also support an external AGP card.
The South Bridge, or Media Communications Processor (MCP), will also be available in two forms. The South Bridge used in a system can be determined by the presence of absence of a 'D' designation to the chipsets name. 'D' chipsets (i.e. either 220D or 420D) contain a Dolby Digital 5.1 encoder, whereas 'non-D' chipsets (i.e. 220 and 420) do not. The South Bridge is virtually identical to that of the X-Box, containing support for 2 ATA100 IDE channels, 6 USB channels, a Modem, an Ethernet controller, an Audio Processing Unit (APU) and the optional Dolby Digital 5.1 encoder. The built-in Ethernet controller is expected to be very high performance, providing a 15% or so performance increase over PCI controllers via the use of nVidia's StreamThru technology. Perhaps the main feature of the South Bridge, however, is the Audio Processing Unit, or APU. The APU is the first fully DirectX 8 compatible sound system for the PC, and is currently the most advanced sound chip available for consumer PC's. The APU is identical to that found in the X-Box, and features the support for 256 simultaneous voices (192 stereo and 64 3D audio streams). 3D effects such as reflection, occlusion and reverb along with (optional) real-time encoding of Dolby Digital AC-3 will be fully handled by the APU, relieving the CPU of all audio tasks.
The nForce chipsets support both 200 and 266Mhz FSB AMD processors (Duron and Athlon) and can contain up to 4 DIMM slots. The chipset drivers are unified (i.e. one driverset contains drivers for the chipset, IDE, graphics, sound etc), and the insertion of an nVidia supplied graphics card will be handled automatically without the need to change drivers. The price of the Crush chipsets is expected to be quite high, at around $50.
Initial benchmarks of the nForce chipset show its performance to be roughly equivalent to VIA's KT266A chipset - i.e. better than AMD's 760 chipset, ALi's MAGiK 1, SiS's 735 and VIA's original KT266. The performance of nVidia's MCP is significantly better than Creative's Soundblaster Live! and graphics performance is around 80% of a GeForce2MX on the nForce 420 and 50-60% of a GeForce2 MX on an nForce 220.
AMD 760MP chipset is the dual processor capable version of the AMD760 released on June 5th. The 760MP consists of the AMD762 North Bridge and AMD766 South Bridge. The 760MP is built on a 0.25 micron process and supports 2 AMD Athlon or Duron CPU's, 4Gb of PC2100 DDR SDRAM (with ECC support), AGP 4X, a 266Mhz FSB and 33Mhz 32 or 64-bit PCI. The AMD762 North Bridge supports two Point-to-Point EV6 busses, on for each processor, giving a 2.1Gb/s link between the North Bridge and each of the CPU's (4.2Gb/s combined bandwidth). The first boards based around the 760MP chipset are expected to be released mid-to-late Q3.
AMD Athlon MP 1 & 1.2Ghz (Palomino) was released on June 5th. The CPU core is identical to the mobile Athlon 4 released on May 14th. See the Athlon 4 Roadmap entry above for additional information about the Palomino core.
AMD Athlon 1.4Ghz, based on the Thunderbird core, was released on June 6th.
AMD Duron 950Mhz, based on the Spitfire core, was released on June 6th.
ATI Radeon clock speed ramps occurred in June. The core and memory clock speeds of Retail 64Mb DDR Radeons was increased from 183Mhz to 200Mhz. The clock speeds of OEM 64Mb DDR Radeons were also increased from 175Mhz to 183Mhz.
Netscape 6.1 PR1 was released on June 14th. This first Beta of 6.1 features greatly enhanced performance and stability, alongside faster page loading, enhanced bookmark management, auto completing URL dropdowns, improved form management, offline mail capabilities for web based mail, a History sidebar and a new "Modern" theme.
Intel Price Cuts for Mobile processors occurred on June 18th.
Matrox G550 was launched on June 19th. The G550 is a slightly enhanced version of the current G450, featuring a slightly increased clock speed (up from the 125Mhz core and 166Mhz memory clock of the G450), a limited Transformation and Lighting (T&L) Engine and the inclusion of 2 texture units per pipeline (the G550, like the G450, contains 2 pixel pipelines). The G550 is pin compatible with the G450, and hence contains the same 64-bit DDR memory interface. The 3D performance of the card is expected to be similar to the Radeon VE and nVidia GeForce2MX-200. The main advantage of the G550 over the G450 is Matrox's HeadCasting technology. HeadCasting is a low-bandwidth video conferencing protocol which makes use of the Matrix skinning function of its T&L engine (in fact this is the only function of the T&L engine, and even this feature is disabled for non-headcasting applications). A digitised photo of the users face and head profile can be emailed to a Matrox associated company which will return a 3D representation of the users head. These representations can be emailed to those taking part in the videoconference. Matrox's video conferencing software sends vertex data alongside the audio stream, which produces a 3D lip synched head on the remote terminal. In addition to the card's 3D featureset, the G550 features a 360Mhz primary RAMDAC, a 230Mhz secondary RAMDAC (for DualHead cards), and two TMDS's. The Millenium G550 is expected to retail for around $125.
Microsoft Visual Studio.NET Beta 2 was released on June 19th.
Intel Pentium III Server (Tualatin core) 1.13Ghz, the 0.13 micron successor to the Pentium III Coppermine, was released on June 21st. The Tualatin core is essentially a 0.13 micron die shrink of the 0.18 micron Coppermine core, although it does offer one additional performance enhancing feature - Data Prefetch Logic (DPL). The idea of Data Prefetch Logic is to predict what is needed in the L2 cache & fetch it from main memory into the cache before the processor requires it. The technology is very similar to the Hardware Prefetch present in the Pentium 4 and Palomino core Athlon. The Server version of this processor comes with 512Kb of on-die L2 cache and is housed in Intel's new FC-PGA2 package. The FC-PGA2 package contains an integrated heat spreader, similar to that present on the Pentium 4 core. The heat spreader provides a larger surface area onto which a heatsink can be attached, providing better heat removal as well as preventing accidental damage to the core when fitting a heatsink. Tualatin CPU's will require motherboards to comply with the VRM8.5 voltage regulation specification (Coppermine = VRM8.4) as well as chipsets which can handle the 1.25v AGTL+ signalling (previous P6 cores required 1.5v signalling).
Intel Pentium III 900Mhz, based on a 100Mhz FSB speed and Coppermine core, was expected to be released in June.
Transmeta Crusoe TM5500 processor was released on June 25th. The TM5500 is initially available in clock speeds of 600, 667 and 733Mhz and is built on a 0.13 micron process. The TM5500 features 256Kb of on-die L2 cache and an improved version of Transmeta's code morphing software (v. 4.2 which is expected to provide a performance boost of around 28% when compared to previous generation processors). The TM5x00 series is expected to run with a core voltage of between 0.9 and 1.3V and dissipate 5.5W at 800Mhz and 7W at 1Ghz.
Transmeta Crusoe TM5800 processor was released on June 25th at clock speeds of 700, 733, 766 and 800Mhz. The TM5800 is the large cache version of the TM5500, featuring 512Kb of on-die L2 cache, but is otherwise identical to the TM5500.
